This invention relates generally to semiconductor devices, and more particularly relates to methods and apparatuses for reducing power consumption of semiconductor devices.
The field of semiconductor memory devices generally and complementary metal-oxide semiconductor (CMOS) devices in particular is enormously active and rapidly developing. Various categories and sub-categories of semiconductor devices are known and commercially available. The ever-increasing popularity and ubiquity of computers and computer-based devices, both in the consumer and industrial realms, is such that the demand for semiconductor memory devices of a variety of different types will continue to grow for the foreseeable future.
In the field of semiconductor fabrication, a persistent issue has been that of current leakage through thin dielectric layers. Those of ordinary skill in the art will appreciate that leakage through the gate dielectrics of field-effect transistors (FETs) is common referred to Fowler-Nordheim tunneling, whereas gate-induced diode leakage (GIDL) occurs at the edge of gate electrode. (This phenomenon is also interchangeably referred to as gate-induced drain leakage.) It is believed that any transistor having a gate overlying source or drain diffusion region to at least some extent is susceptible to GIDL. As gate dielectrics, which are typically formed of silicon oxide, become increasingly thinner due to continued scaling of semiconductor structures in pursuit of faster and more efficient operation, problems relating to GIDL present an ongoing challenge to circuit designers.
GIDL results from the generation of electron-hole pairs in the surface of the depletion region of a FET along the area where the gate conductor overlies the drain diffusion region (separated by a dielectric layer) when the device is biased such that the drain potential is greater than the gate potential (for NMOS devices) or lower than the gate potential (for PMOS devices). FIG. 1 is a side cross-sectional illustration of a portion of a FET 10 including a gate conductor 12 and a drain diffusion region 14 formed on a silicon substrate 16. As shown in FIG. 1, it is often the case that a portion of the drain diffusion region 14 of a FET is positioned under the gate conductor 12. As a result, for an NMOS device, if the gate conductor 12 is at 0 volts and the drain diffusion region 14 is at a positive voltage, there is volume 18 of carrier generation due to the electric field induced by the drain-to-gate voltage differential xcex94VGIDL. Such carrier generation tends to impair device performance. In addition to increasing standby power, in the context of dynamic random access memory devices, GIDL can degrade data retention time, such that the maximum time between refreshes of a memory array is undesirably decreased.
Various approaches have been proposed in the prior art for overcoming GIDL phenomena in semiconductor devices. Prominent among these are strategies for either increasing the thickness of the gate oxide in a FET, or for otherwise making the gate oxide more resistant to leakage current; various doping strategies for minimizing GIDL effects have also been proposed. Various approaches are proposed, for example, in U.S. Pat. No. 6,294,421 to Gonzalez et al., entitled xe2x80x9cMethod of Fabricating Dual-Gate Dielectric;xe2x80x9d in U.S. Pat. No. 6,097,070 to Mandelman et al, entitled xe2x80x9cMOSFET Structure and Process for Low Gate Induced Drain Leakage (GILD) [sic];xe2x80x9d in U.S. Pat. No. 6,090,671 to Balasubramanyam et al., entitled xe2x80x9cReduction of Gate-induced Drain Leakage in Semiconductor Devices;xe2x80x9d and U.S. Pat. No. 6,297,105 to Guo, entitled xe2x80x9cMethod of Forming Asymmetric Source/Drain for a DRAM Cell.xe2x80x9d Each of the foregoing patents is hereby incorporated by reference herein in its entirety.
Despite semiconductor designers"" ongoing efforts to stabilize and minimize the power consumption of semiconductors and in particular to minimize the undesirable phenomenon of GIDL, there nevertheless continues to be an ongoing need for improvements in the field. Among other considerations, the various proposed strategies for alleviating GIDL phenomenon in semiconductor devices often suffer to greater or lesser extents from the disadvantages of unduly increasing device size, adding complexity to the fabrication process, or degrading device performance.
Those of ordinary skill in the art will further appreciate that problems with GIDL are exacerbated in semiconductor devices which utilize charge pumps which are capable of providing voltages more positive than the most positive externally-applied supply voltage and/or more negative than the most negative externally-applied supply voltage. Such charge pumps are well known in the art, as are their numerous advantageous applications in semiconductor devices such as memory devices and the like. Charge pumps may be utilized to provide a bias voltage for a substrate of an integrated circuit, or for providing greater output voltage swings. Examples of charge pump circuits are disclosed in U.S. Pat. No. 5,038,325 to Douglas et al., entitled xe2x80x9cHigh Efficiency Charge Pump Circuit,xe2x80x9d and U.S. Pat. No. 5,126,590 to Chern, entitled xe2x80x9cHigh Efficiency Charge Pump.xe2x80x9d The ""325 and ""590 patents are commonly assigned to the assignee of the present invention and are hereby incorporated herein by reference in their respective entireties.
As noted in the ""590 patent, most charge pumps comprise some variation of the basic charge pump 20 shown in the schematic diagram of FIG. 2. The basic charge pump 20 configuration includes a ring oscillator 22 that provides a square wave or pulse train having voltage swings typically between ground and the most positive external power supply voltage, VCC. An inverter 24, buffer amplifier, or Schmitt trigger circuit may be used to sharpen the edges of the oscillating output signal of the ring oscillator 22. A capacitor 26 is discharged into the substrate 34 through diode-connected transistors 28 and 30. (Typically the drain and gate of a diode-connected transistor are coupled together to form the anode of a diode and the source forms the cathode of the diode.) Transistor 28 is coupled to the external power supply voltage, VCC, at terminal 32. When the ring oscillator 22 produces a voltage close to ground, circuit node 36 is approximately at the voltage of the power supply minus a transistor threshold voltage, VCC-VT. When the ring oscillator 22 produces a voltage close to VCC, the incremental charge on the capacitor 26 is delivered to the substrate 34. Capacitor 26 is prevented from discharging to any other circuit node by the reverse bias on diode-connected transistors 28 and 30.
As noted above, because charge pumps produce on-chip voltages more positive and/or more negative than the respective positive and/or negative supply voltages, integrated circuits incorporating charge pumps are even more susceptible to problems associated GIDL.
In view of the foregoing considerations, the present invention is directed to a method and apparatus for reducing the effects of GIDL in semiconductor devices, especially semiconductor devices incorporating charge pump circuits.
In one embodiment of the invention, the invention involves the multiplexing of a pumped voltage and a regulated voltage in a pumped voltage supply circuit, such that functional elements of a semiconductor device are provided with a pumped voltage during operationally active periods and are provided with a slightly reduced regulated voltage during idle or standby operational periods. (As used herein, the terms xe2x80x9cidlexe2x80x9d or xe2x80x9cstandbyxe2x80x9d modes shall be understood to refer to intervals where a semiconductor device is powered-up, but not active. In the context of semiconductor memory devices, such a situation would exist when the memory device is powered up, but no memory access cycles are occurring.)
In a disclosed embodiment, a voltage pump generates a pumped voltage and a voltage regulator provides a regulated voltage, where the pumped voltage is characterized as being either more positive than the most positive externally-applied positive voltage supply signal or more negative than the most negative externally-applied negative voltage signal. The pumped voltage and the regulated voltage are applied to respective inputs of a multiplexer receiving a select signal. In response to the state of the select signal, the multiplexer outputs either the regulated voltage or the pumped voltage.
In an alternative embodiment, a non-regulated form of the externally-applied voltage is utilized in place of the regulated voltage. In any case, the multiplexer is conditioned to selectively output either the pumped voltage or the regulated or non-regulated voltage. The output of the multiplexer is provided to the input of an array network for distribution of the incoming signal to functional elements of the semiconductor device. Preferably, the multiplexer is controlled by a select signal whose state is appropriate to cause the multiplexer to apply the pumped voltage to the array network during active operational cycles of the semiconductor device, and to provide the regulated or non-regulated voltage to the array network during idle or standby operation of the semiconductor device.
In one embodiment of the invention, the multiplexer is configured to incorporate at least one current-limiting element to limit the current supplied to the array network when the regulated or non-regulated voltage is applied thereto. One or more long length (long L) transistors may be employed as the current-limiting elements.